The development of the Complementary Metal-Oxide Semiconductor (CMOS) device technology has been supporting the electronics industry and engineers are adopting finer CMOS design rules at an unprecedented pace in order to further improve the performance. As for generations of CMOS devices, which are expressed in terms of technology node, volume production of the 45-nm node has been started, the 32-nm node technology has been developed, and development of the next generation or the 22-nm node has begun. The feature sizes of devices become smaller and smaller and the gate lengths of MOS transistors are now 35 nm or less.
As the feature size of devices becomes smaller, processes such as the photolithography and etching processes are becoming more difficult to perform. Source-drain impurity profiles are designed so that devices operate even when gate pitches are reduced. Sidewalls are used primarily to set an offset for regions such as source-drain regions to gate electrodes. It is known that a problem of variations in threshold voltage arises as the gate length of a MOS gate transistor decreases. The phenomenon is called the short-channel effect.